1. Field of the Invention
The present invention relates to a method for fabricating capacitors of a semiconductor device, and more particularly to a method for fabricating capacitors having an increased surface area in accordance with an etch process using a difference in etch selectivity ratio between doped and undoped layers in a highly integrated semiconductor device, thereby ensuring a high capacitance.
2. Description of the Prior Art
The recent high integration trend of semiconductor devices inevitably involves a reduction in cell dimension. However, such a reduction in cell dimension results in difficulty in forming capacitors having a sufficient capacitance. This is because the capacitance is proportional to the surface area of the capacitor.
In the case of a dynamic random access memory (DRAM) device including a metal oxide semiconductor (MOS) transistor and one capacitor, in particular, it is important to reduce the area occupied by the capacitor and yet obtain a high capacitance of the capacitor, for the high integration of the DRAM device.
For increasing the capacitance, various research has been conducted. For example, there have been known use of a dielectric material exhibiting a high dielectric constant, formation of a thin dielectric film, and formation of capacitors having an increased surface area, taking into consideration the fact that the capacitance of the capacitor is proportional to the area of the capacitor and inversely proportional to the thickness of the dielectric film constituting the capacitor.
However, all of these methods have their own problems. Although various materials, such as Ta.sub.2 O.sub.5, TiO.sub.2 or SrTiO.sub.3, have been proposed as the dielectric material exhibiting a high dielectric constant, their reliance and thin film characteristics have not been confirmed. For this reason, it is difficult to use such dielectric materials for semiconductor devices in practical situations. The reduction in the thickness of dielectric film results in damage to the dielectric film severely affecting the reliance of the capacitor.
In order to increase the surface area of the capacitor, a cylindrical capacitor structure has also been proposed. Now, a method for fabricating such a cylindrical capacitor structure will be described.
In accordance with this method, a semiconductor substrate, which has a lower insulating layer, is prepared. A contact hole is then formed at the semiconductor substrate in accordance with an etch process using a contact mask so as to expose a desired portion of the semiconductor substrate. Over the resulting structure, a first conduction layer is formed. The first conduction layer is in contact with the semiconductor substrate through the contact hole. An oxide film pattern is then formed on the first conduction layer in accordance with an etch process using a storage electrode mask. Using the oxide film pattern as a mask, the first conduction layer is then etched. At this time, the lower insulating layer is used as an etch barrier. Over the resulting structure, a second conduction layer is deposited to a desired thickness. Subsequently, the second conduction layer is anisotropically etched, thereby forming second-conduction layer spacers respectively on the side walls of the oxide film. These spacers are in contact with the first conduction layer. Thereafter, the oxide film is removed, thereby forming a cylindrical storage electrode. At a subsequent step, a dielectric film and plate electrode are formed on the cylindrical storage electrode. Thus, a cylindrical capacitor is obtained. Using such a method, a capacitor having a plurality of cylinder structures can be formed. However, this method involves a difficulty to ensure a sufficient capacitance for highly integrated semiconductor devices.